delayed control-transfer

A technique used on the {SPARC} which attempts to reduce the

effect of {pipeline break}s by executing the instruction after

a branch instruction (the "delay instruction" in the "delay

slot"). If there is no useful instruction which can be placed

in the delay slot then the "annul bit" on the control-transfer

instruction can be set, preventing execution of the delay

instruction (unless the control-transfer is conditional and is

taken).

If the delay instruction is also a control-transfer

instruction then it gets more complicated. Both

control-transfer instructions are executed (but not the

following instruction) and, assuming they are both taken,

control is transferred briefly to the destination of the first

and then immediately to the destination of the second.